Importance of Stencil for PCB Assembly

The surface mount assembly process uses a stencil as a gateway to an accurate and repeatable solder paste deposition. A stencil is a thin sheet or foil of brass or stainless steel with a circuit pattern cut into it, matching the positional pattern of surface mount devices (SMD) on the printed circuit board (PCB) for which the stencil is to be used. After accurately positioning and matching the stencil over the PCB, a metal squeegee forces solder paste through the apertures of the stencil to form deposits on the PCB for holding SMDs in place. The solder paste deposits, when passed through the reflow oven, melt and secure the SMDs to the PCB.
The design of the stencil, especially its composition and thickness and the shape and size of its apertures, determines the size, shape, and positioning of the solder paste deposits and this is crucial to ensuring a high-yield assembly process. For instance, the foil thickness and the aperture opening size define the volume of paste deposited on the board. An excess of solder paste causes balling, bridging, and tomb-stoning. Low amounts of solder paste cause dry solder joints. Both compromise the electrical functionality of the board.
Optimum Foil Thickness
The types of SMDs on the board define the optimum foil thickness. For instance, component packages such as 0603 or SOICs with a 0.020” pitch require rather thin solder paste stencils, whereas a thicker stencil is more suitable for components such as 1206 or SOICs of 0.050” pitch. Although stencil thickness for solder paste deposition ranges from 0.001” to 0.030”, the typical foil thickness that a majority of boards use ranges from 0.004” to 0.007”.
Technologies for Making Stencils
At present, the industry uses five technologies for making stencils—laser-cut, electroformed, chemically etched, and hybrid. While the hybrid technology is a combination of chemical etching and laser-cutting, chemical etching is very useful for making step stencils and hybrid stencils.
Chemical Etching for Stencils
Chemical milling etches metal masks and flexible metal mask stencils from both sides. As this etches not only in the vertical direction but also laterally, it causes undercutting, and makes the openings larger than desired. As the etching proceeds from two sides, the tapering on the straight wall causes the formation of an hourglass shape, leading to extra deposits of solder.
As etching the stencil openings does not produce a smooth result, the industry uses two methods for smoothening the walls. One of them is electropolishing, a microetchng process, and the other is nickel plating.
Although a smooth or polished surface helps paste release, it may also cause the paste to skip the surface of the stencil rather than roll with the squeegee. Stencil manufacturers address this problem by polishing the aperture walls selectively, but not the stencil surface. While nickel plating improves stencil smoothness and the printing performance, it reduces the aperture opening, which requires artwork adjustment.
Laser Cutting for Stencils
Laser cutting is a subtractive process, where Gerber data is fed to a CNC machine that controls the laser beam. The laser beam starts from inside the boundary of the aperture and traverses to its perimeter, while completely removing the metal to form the apertures, one aperture at a time.
Several parameters define the smoothness of the laser cut. This includes cutting speed, beam spot size, laser power, and beam focus. Typically, the industry uses a beam spot of about 1.25 mils, which cuts very accurate aperture sizes over a wide range of shape and size requirements. However, laser cut apertures also require post-processing treatments just as chemically etched apertures do. Laser cut stencils require electropolishing and nickel plating to smoothen the inside walls of the aperture. As the aperture size reduces during the latter process, the laser cut aperture size must be suitably compensated.
Aspects of Printing with a Stencil
Printing with a stencil involves three distinct processes. The first is the aperture-fill process where the solder paste fills the aperture. The second is the paste transfer process, where the paste accumulated in the aperture transfers to the PCB surface, and the third is the positional location of the deposited paste. The three processes are vital to achieving the desired result—depositing a precise volume of solder paste (also called a brick) to the correct location on the PCB.
Filling the stencil aperture with solder paste requires a metal squeegee blade forcing the solder paste into the aperture. The orientation of the aperture with respect to the squeegee blade affects the fill process. For instance, apertures oriented with their short axis in the direction of the blade stroke fill better compared to those with their long axis oriented to the blade stroke. Additionally, as squeegee speed influences aperture fill, lower squeegee speeds achieve better fills for apertures with their long axes oriented parallel to the stroke of the squeegee.
The edge of the squeegee blade also influences the way the paste fills the aperture of a stencil. The usual practice is to print applying minimum squeegee pressure while maintaining a clean wipe of the solder paste on the stencil surface. Increasing the squeegee pressure may damage both the squeegee blade and the stencil, while also causing paste smearing below the stencil surface.
On the other hand, lower squeegee pressure may not allow release of paste through a small aperture, resulting in insufficient solder on the PCB pad. Additionally, paste left on the side of the squeegee near large apertures will likely be pulled down by gravity, resulting in deposition of excess solder. Therefore, a minimum amount of pressure is necessary, which will achieve a clean wipe of the paste.
The amount of pressure to be applied also depends on the type of solder paste being used. For instance, Teflon/nickel-coated squeegee blades require about 25-40% more pressure when using lead-free solder paste than that required for tin/lead paste.
Performance Issues with Solder Paste and Stencils
Certain performance issues related to solder paste and stencils are:
  • Thickness of the stencil foil and the aperture size determine the potential volume of solder paste deposited on the PCB pads
  • The ability of the solder paste to release from the aperture walls of the stencil
  • Positional accuracy of the solder brick printed on the PCB pad
During the print cycle, as the squeegee blade travels across the stencil, solder paste fills the stencil aperture. During the board/stencil separation cycle, the paste releases to the pads on the board. Ideally, all the paste that filled the aperture during the print process should have released from the aperture walls and transferred to the pad on the board, forming a complete solder brick. However, this transfer amount depends on the aspect ratio and area ratio of the aperture.
For instance, with an area of the pad greater than two-thirds the area of the inside aperture wall, the paste can achieve a release of better than 80%. This means reducing the stencil thickness or increasing the aperture size can give a better paste release with the same area ratio.
The ability of the solder paste to release from the aperture walls of the stencil also depends on the finish of the aperture walls. With electropolished and/or electroplated laser-cut apertures, the paste transfer efficiency improves. However, transfer of solder paste from the stencil to the PCB also depends on the adhesion of the paste to the aperture walls of the stencil and on the adhesion of the paste to the pad on the PCB. For a good transfer the latter should be greater, which means the printability depends on the ratio of the stencil wall area to the open face area, while ignoring minor influences such as the draft angle of the wall and its roughness.
The positional and dimensional accuracy of the solder brick printed on the PCB pad depends on the quality of the transferred CAD data, the technology and methods used to manufacture the stencil, and the temperature of the stencil during its use. Moreover, the positional accuracy also depends on the alignment methods used.
Framed Stencils or Glue-In Stencils
Framed stencils are the strongest form of laser-cut stencils available and are designed for high-volume screen-printing during production runs. These are permanently mounted in a stencil frame with a mesh border tightly stretching the stencil foil taut in the frame. Framed stencils with smooth aperture walls are recommended for Micro BGAs and for components with 16 Mil pitch and below. Framed stencils offer the best positional and dimensional accuracy when used under controlled temperature conditions.

Fig.3: Framed Stencil

Frameless Stencils

For short runs or prototype PCB assembly, frameless stencils offer optimum solder paste volume control. They are designed to work with a stencil tensioning system, which are reusable stencil frames such as universal frames. As the stencils are not permanently glued into a frame, they are significantly cheaper than framed stencils and take up considerably lower storage space.
For achieving good printing results with a stencil, a variety of factors must form a right combination. These include:

  • The right paste material—correct metal content, viscosity, the largest powder size, and lowest possible flux activity
  • The right tools—proper stencil, printer, and squeegee blade
  • The right process—good registration, and clean sweep.

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Taking Care of Warpage and Thermal Profile Issues during Assembly

A warped printed circuit board (PCB) is one that does not sit true on a flat desktop. Although there are several reasons as to why this should happen, there are two specific causes that cause board warping. One of them is layout related, while the other is process related. If the PCB is found to be warped before the start of assembly, the problem has occurred between layout and fabrication. If the PCB was flat before, but was found warped after assembly, then the problem is likely between fabrication and assembly. However, some fabrication problems will not show up until the PCB has passed through the reflow oven.

Fig.1: Warped PCB

Settling on the root cause is generally an iterative process. To discuss the issue with the fabrication or assembly shop, collecting some additional information is necessary. This could be the amount of warpage per inch, size of the board, and its thickness. Along with this information, it may be necessary to consider copper pours, placement of components, and their sizes, provided the board design is in-house.

With the above information, a discussion with the design house, fabrication, or the assembly shop may serve to highlight the issue and cause of the warpage. Once the design issue is ruled out, it may be necessary to determine if it relates to fabrication or assembly, which leads to the next step of determining a solution to the problem.

Design Issues Contributing to Warping

There can be several obscure design issues contributing to PCB warping. To be able to eliminate them before moving over to fabrication or assembly, it is necessary to know the major design contributors:

  • Odd shapes or large cutouts—can cause considerable warping at any stage
  • Thin board—related to number and size of components can lead to warping after assembly
  • Heavy components grouped together—can cause warping during assembly. The thermal mass acts like a heat sink does, leading to uneven expansion and non-even soldering on the PCB
  • Uneven copper pour—although copper and Polyimide/FR-4 are matched for thermal expansion, the matching is not exact. The dissimilarity is magnified for a large copper pour on one side or on a corner, leading to warping either during fabrication or during assembly. This may require the designer change over the solid copper pour to crosshatch for reducing the warpage.

Fig.2: Solid Copper Pour & Crosshatch

Assembly Related Issues Contributing to Warping

Polyimide and FR-4 both absorb moisture from the environment. If a stack of bare boards have been stored for some time before assembly, it is customary to bake them for at least 3 hours at 80-150°C to drive out the moisture. Assembly can start once they are cooled to room temperature. Some board suppliers vacuum seal their products with a desiccant before shipping, and if the complete package is not consumed in one assembly run, it is necessary to reseal the balance along with the desiccant.

Warping in large boards may be related to the orientation as the boards enter the reflow oven. Placing the larger dimension parallel to the conveyor of the oven can prevent uneven heating between the edge of the PCB and its middle. Large boards may require additional support at the center of the PCB, and adding carriers may be necessary. Similar support may also be required for flexible PCBs during reflow.

Fig.3: Breakaway PCB

Fig.4: V-Groove on PCB

Often small PCBs are grouped together to form panels for more efficient assembly. After assembly, operators manually separate them into individual PCBs. Manufacturers follow two methods for easing the process of separation—breakaway and v-scoring. In breakaway, most of the material between the smaller PCBs is cut away, leaving them joined by only small lands. If the panelization is large, these cutouts could lead to warping. V-scoring is an alternative method where instead of removing a part of the PCB, a v-shaped groove forms the separation line. This prevents warping of the panel during assembly, but allows the operators to separate the boards easily.

Fig.5: Reflow Oven

Although 3-zone reflow ovens were adequate for tin/lead soldering, with the advent of RoHS processes and lead-free soldering, reflow ovens operate at higher temperatures. Moreover, to reduce thermal shock to the PCB and components when in reflow, the temperature is gradually built up over several zones, sometimes as many as six to nine—with greater possibilities of error in the settings in one or more of the zones.

Warping may also be caused by oven loading. If the thermal profiling for a specific PCB was done for a certain number of boards in the reflow oven at the same time, the oven temperature may rise when in a subsequent run the number of boards is smaller. As the number of boards in the oven influences the thermal load, the thermal demand may not be adequate to maintain the typical reflow profile for the smaller batch of PCBs.

Clogging of airflow outlets of the reflow oven may also cause a change in the temperature-time profile for a specific PCB, resulting in uneven heating and consequently to warping. Likewise, clogging of orifice plates due to flux accumulation may also limit the forced convection flow, causing the boards to heat up unevenly.

Preventing Warping of PCBs

For PCBs meant for surface mount technology, the IPC-6012 standard defines the maximum camber and twist or warping to 0.75%, while for other types (through-hole technology) this is relaxed to 1.5%. However, most electronic assembly plants dealing with double/multilayer boards prefer to limit warping to between 0.7 and 0.75%. Rigid PCBs with thicknesses of around 1.6 mm and using SMDs and BGAs can only stand warping to the extent of 0.5%, while others using PoP can handle warpages of only 0.3% or less.

Storing PCBs properly before assembly is crucial in preventing warpage. Stacking PCBs on their edge cannot guarantee they will be vertical all the while, and the combined weight of the PCBs will ultimately cause a camber. Therefore, storing them horizontally on a flat surface is essential.

It is usual for PCBs to absorb moisture from the surroundings. Storing them in an area where the temperature and humidity is under control is the ideal solution. Where it is impractical to control the environment within the entire store, use of desiccants to control the moisture within a sealed container may also help in preventing PCBs from acquiring moisture during storage.

As PCB fabricators use heat to form multilayer boards, re-application of heat to warped bare boards should be helpful in straightening them as well. This may require heavy-pressing the boards between heated smooth steel plates for 3 to 6 hours and baking the PCBs 2 to 3 times.

Impact of Quality of PCBs on Assembly and Product Life Cycle

Irrespective of whether the electronic product is a next generation computer system or a simple mobile handset, inside it there is a printed circuit board (PCB). Engineers design PCBs to support and connect electronic components and other hardware inside the product. The PCB usually has conductive pathways holding the electronic components together by soldering, a process for attaching different metals such as tin, silver, gold, and copper together. The process also serves to interconnect all hardware within the product.
Fig.1: Printed Circuit Board
Printed Circuit Boards (PCBs) must meet three basic requirements to be acceptable for assembly, and to establish products with longevity. According to Clyde Coombs, the author of “The Printed Circuits Handbook,” these three basic requirements are:
  • The physical form of the PCB should match its intended design. Dimensions and placement of interconnection points and the coating on these interconnection points must allow proper component assembly
  • The PCB must provide proper interconnection between components
  • The circuit board must provide adequate insulation between interconnection points that are not to be connected
The above three items must be acceptable and remain of high quality all through the expected life of the product. As there can be several details related to the three requirements, defining the requirement for acceptability and quality for the PCB suppliers is essential to ensure they meet the three requirements. Properly implemented, the quality and acceptance criteria provide all parties a clear picture of the expectations.
Industrial Standards for PCBs
Conforming to industrial standards has the advantage of establishing a common foundation—creating level playing fields—to allow all participants to adhere to as a minimum. Adhering to industrial standards leads to avoiding many chances of failure. Everyone can easily develop knowledge about a common specification rather than interpreting endless numbers of individual company specifications. However, companies may be forced to move beyond the standards for various reasons, as their designs need to advance further than the scope defined by the standards.
Users evaluate PCB quality based on their use in products falling into three categories, called classes. These are:
Class 1: General Electronic Products, such as consumer electronic product
Class 2: Dedicated Service Products, such as those providing uninterrupted service
Class 3: High Reliability Products, such as those providing continuous service
Typically, manufacturers determine the class appropriate for their product. For instance, if a toy manufacturer wants PCBs that meet class 3 requirements, they must be willing to pay for the extra level of reliability.
Internationally, the IPC-6011 standard defines the generic performance specifications for PCBs. According to IPC-6011, the supplier of the PCB is responsible for verification of compatibility with the specifications, master drawings and patterns, and the specific manufacturing facilities and processes. In short, the supplier must ensure the PCB meets the requirements of the procurement documentation.
By default, the IPC-6011 standard applies to all circuit board types. However, this needs to be supplemented by performance specifications containing the requirements of the chosen technology such as:
IPC-6012: for Rigid PCBs
IPC-6013: for Flexible (Flex) PCBs
IPC-6014: for PCMCIA PCBs
IPC-6015: for MCM-L PCBs
IPC-6016: for HDI PCBs
IPC-6017: for Microwave PCBs
Although IPC-6012 is the most common specification used in documentation packages, manufacturers can specify the requirements according to the PCBs their electronic products use.
Acceptability of PCBs
Sometimes, it may be impossible to establish criteria for non-conformance from descriptions alone, such as from IPC-6012 and others. To circumvent this, the standard IPC-A-600 has been developed, which contains illustrations and photographs, and offers three levels of quality for each specific characteristic: Target, Acceptable, and Non-Conforming Conditions. Furthermore, the characteristics are divided into two general groups:
Externally Observable Conditions: these are features or imperfections visible on the exterior surface of the board and it is possible to evaluate them.
Fig.2: Illustration of Void within a Via
Fig. 2 is the image of a copper plating acceptable for a product of class 2. The acceptance criteria for the plating are:
  • Not more than one void in any hole
  • Not more than 5% of the holes have voids
  • Any void is not greater than 5% of the length of the hole
  • The void is less than 90 of the circumference of the hole
Internally Observable Conditions: these features or imperfections can only be detected, examined, and evaluated after a micro sectioning of the PCB.
Fig.3: Micro-Section of a Via Hole
Fig. 3 is the image of a plated hole, showing in micro-section the thickness of copper and insulating layers, along with highlighting of material imperfections, if any.
The thickness of copper and insulation layers must match those specified in the design documents. Overall thickness of the board is also an important criterion.
Typically, such micro-sections are performed on coupons with the same characteristics as possessed by the actual board design. This avoids destroying a good board while testing.
General Defects in PCBs and Their Effect on Assembly
Board Warpage: If the board is not perfectly flat, it can cause several problems in the assembly process. This could be a local change in the PCB thickness or an issue of coplanarity of the PCB. It can result in potential opens from tilted components known as the teeter-totter effect, or from dropped solder connection, such as with a BGA joint. A solder joint may also potentially lose reliability from stretching. In general, leadless devices are more susceptible to PCB warpage.
Fig.4: Ball Drop & Stretched Joints
Fig.5: Effect of Warpage on Leadless Devices
With a warped board, there may also be an issue with controlling the volume of paste deposition, both for solder paste and adhesive. Warpage usually results in the stencil being unable to sit flat all over on the PCB surface, leaving gaps in between the stencil and board in certain areas. While this may result in uneven printing of solder paste across the board, there may be insufficient adhesive dispensing or adhesive may be skipped altogether in those areas.
While printing, gaps between the stencil and board may fill up with solder paste. This may cause a smear, wet bridge, or excess deposit of solder paste. Sometimes, paste fringing on the stencil after printing may cause unnecessary smears on the next print.
Fig.6: Unsoldered Leads
Fig.7: Tombstoned Passive Component
Uneven deposition of solder paste may result in insufficient volume being present, showing up as solder covering the pad, but with metallization showing through. As there is insufficient paste to touch the component leads, it results in unsoldered leads after reflow. For small packages, which usually decrease the total tolerance of PCB and assembly process, this may also lead to paste misalignment, resulting in cocking or tombstoning of passive chip components, impacting process yields.
During waves soldering, if via holes are unfilled and the board has warpages, the assembly can potentially lift off the wave, resulting in areas remaining unsoldered.
Solder Mask Issues: Improperly applied solder mask may cause reliability issues during assembly. One of the major issues is the missing solder mask dam between two neighboring solder pads, leading to a potential solder short or bridging during a wave soldering operation.
Fig.8: Missing Solder Mask Dam
Fig.9: Shifted Solder Mask
Normally, the solder mask is required to cover a pad all around. If there is a shift or misregistration, the solder mask may not cover the land fully, and form a pocket next to the land, exposing the neighboring pad or track. This area can subsequently fill with solder paste and create a whisker or bridge shorting the pads with the neighboring pad or track.
Another reliability issue arising from improperly applied solder mask is a smear on the pad itself causing solderability issues. This prevents solder from wetting the smeared land properly during reflow or wave soldering, leaving the pad non-solderable.
Fig.10: Solder Mask Smear on Pad
Fig.11: Solder Ball
If the solder mask remains under-cured, it can lead to product reliability issues, as areas of under-cured solder mask can trap processing residues and contribute to electrical leakages or to electromechanical migration failures. Improperly cured solder resist may also allow solder to accumulate in the form of balls during wave soldering, leading to potential electrical shorts.
Issues with HAL Boards: Non-coplanar or uneven solder surfaces are a major issue for HAL finish boards. A very thin coating of HAL may lead to migration after the first reflow operation, exposing copper and leading to poor solderability in subsequent reflows.
Fig.12: Uneven HAL Solder
Fig.13: Thin HAL Coating
As stencil openings normally do not match the pad perfectly, some parts of the stencil may rest on the excess solder deposit, leaving the other area of the stencil lifted away from the board. This allows solder paste to squeeze into the gap between the stencil and the board, creating issues similar to those on boards with a warpage.
Fig.14: Solder Bridge
Fig.15: Grainy Solder Joint
Non-coplanarity of HAL boards may also lead to bumps of solder being left on pads causing the stencil to lift up and solder paste filling the underneath gap. During reflow, the excess solder may cause adjacent lands to bridge or whiskers to form between adjacent fine-pitch components. The flux in the solder paste may not be adequate for the total amount of solder from the paste and that left on the pad by the HAL process, and this may result in a grainy or disturbed joint.
The PCB being an electromechanical item in a product has many opportunities for failure. PCB quality is a huge subject with numerous possibilities for imperfections affecting assembly and the product life cycle. Starting from warping of the PCB surface to via failure to under-etching of traces, each aspect of PCB quality can bring the product to an abrupt halt much before its intended life cycle is over.
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PCB POWER launched online High Quality Power Stencils

PCB POWER has now decided to start shipping high quality laser stencils for its customers. Well-known for being ultimate in class service and reliability, PCB POWER will now be providing its customers stencils on demand.  The customers would be free to choose the type of stencils (framed or frameless) they want and place an order for the same online. They can also avail the benefit of a separate price calculator having user friendly concept created for this purpose.
Stencils are used in assembly of high reliability surface mount component assembly. For ultimate accuracy, we manufacture our stencils using fine quality steel and ultra accurate cutting technology.
Customers can now conveniently order PCBs along with Stencil. For further details, please login on your account
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What Are Vias And Why Do You Need Them?

Just as a printed circuit board (PCB) is a means to allow interconnection of different components, vias are means to interconnect different layers on and within the multilayered PCBs. Also, just like there are various types of PCBs, there are multiple types of vias with their own functionality. Simply put, vias are Plated-Through Holes (PTHs) passing through one or more layers in a PCB, connecting traces on its way. IPC defines seven types of vias in IPC-50M, Terms and Definitions for Interconnecting and Packaging Electronic Circuits. These are:
Type I: Tented Vias—vias that have a mask material applied, bridging over them, with no additional material inside the holes.
Type II: Tented and Covered Vias—type I vias with a secondary covering of mask material over and above the tented vias.
Type III: Plugged Vias—vias with material partly penetrating into the via holes.
Type IV: Plugged and Covered Vias—type III vias with a secondary material covering the vias.
Type V: Filled Vias—vias with material fully penetrating and encapsulating the via holes.
Type VI: Filled and Covered—type V vias with a secondary material covering the vias.
Type VII: Filled and Capped—type V vias with a secondary metalized coating covering the vias.
                                                            Fig. 1: Close-up of a Via
Although small and sometimes very small, vias are extremely important parts of the circuit board landscape. In fact, in the world of surface mount components, vias are the only means to interconnect copper traces on different layers on a PCB, where earlier, leads of components would do the job when soldered on both sides of a two-layer PCB. The only difference between plated-through holes and vias is no component lead will ever pass through the hole of a via.
                                                        Fig. 2: Different Types of Vias
Each of the seven types of vias classified above may be further subdivided into three types depending on their functionality—blind or hidden vias, buried vias, and through hole vias. As the name suggests, through hole vias travel through the board, connecting traces on the outermost layers, and if required, on the inner layers as well. Blind vias start on the surface on one side of the board, but do not extend to the other side, finishing on one of the internal layers instead. Buried vias remain completely encapsulated within the board, and none of their ends extend to any of the outer surfaces of the board.
Most vias in high-density boards have very small-diameter holes, and are called micro-vias. Manufacturers use different tools such as ultrasonic beams and lasers to drill these holes. Usually, micro-vias are filled with a conductive material to facilitate connecting with the pad on the other layer. However, this can lead to issues with unequal expansion as explained later.
Tented Vias
                                                                  Fig. 3: Tented Vias
The word “tenting” in the PCB industry originally meant the solder mask would enclose the via fully in the form of a skin or tent over the hole. This was difficult for manufacturers to achieve with liquid photo-imageable (LPI) solder mask, as the success of the process was dependent on the diameter of the hole and surface tension of the LPI. With the introduction of dry film solder mask, manufacturers achieved tenting easily, but the process was more expensive.
With LPI, tenting caused the mask to cover the pad and enter the hole partly. However, this was not consistent, as some vias remained unplugged, and others had the tent broken over the hole, covering only the annular ring or pad. Therefore, as per requirement, manufacturers resorted to plugging vias with conductive or non-conductive materials before tenting with LPI.
Tenting is useful for reducing the number of exposed conductive pads present on the PCB, and helps in reducing the likelihood of shorts from solder bridging during the assembly process. In the case of SMT pads, tenting helps to reduce paste migration away from the pads of SMD components when vias are placed either on the ends of their pads or on the dog-bones meant for BGAs.
Additionally, tenting is helpful whenever vias are placed close to SMT pads, especially in areas within the BGA package, where shorts can easily happen under the component during reflow, making rework difficult and time-consuming. Covering the tented via with a secondary coating of solder mask often helps,
Disadvantages of Incomplete Tenting
                                                             Fig. 4: Incomplete Tenting
Although tenting of vias by primary LPI solder mask is advantageous as it is only a single step process, the process cannot guarantee complete tenting, resulting in long-term reliability issues. Successful tenting by screen coating depends on the size of the hole, surface tension of the liquid mask, and the board thickness. As no surface finish is applied to the via barrel before tenting, incomplete tenting may cause entrapments. Usually, this is chemical entrapment from preclean lines when enhancing surface finish.
Preclean lines subject surface finishes to a micro-etching process, allowing micro-etchants to be trapped in the open vias, where the chemical crystallizes rapidly to generate copper-sulfate crystals. Over time, these crystals etch away the copper in the barrel, causing long-term reliability issues. For instance, the gold of the ENIG finish could form a galvanic cell with the exposed copper near the top of the via in the presence of the micro-etchant chemical, thereby accelerating the process of etching.
Incomplete tenting may also cause solder paste to wick into the via, leaving insufficient paste to complete the actual soldering. In the case of BGAs, localized thermal energy may cause the LPI solder mask to lift between the ball and the via capture pads, as the distance between them is very short, causing solder shorts.
Above issues with incomplete tenting has led to manufacturers plugging vias with solder mask or some other non-conductive or even conductive materials. The plugged via does not require surface finish to be applied to the via barrel, but does ensure that subsequent application of the LPI mask leaves all the vias fully tented.
Vias Plugged with Non-Conductive Fill
For vias plugged with solder mask or similar non-conductive epoxy material, the manufacturer has to ensure the via is completely plugged and sealed, and its annular ring is fully covered. This is a common practice when using BGA SMD pads to prevent solder wicking into the via creating poor or non-existent solder joints.
                                                               Fig. 5: Active Pad
However, with BGA packages becoming tighter, it is becoming increasingly difficult placing vias on standard ‘dog-bone’ land patterns for transferring signals to other layers. This difficulty has led to vias being drilled directly into the pads of the BGA footprint. The process is known as via-in-pad, and allows much simpler routing. Although this requires the via hole to be fully plugged, it also requires the surface of the plugged via to be plated over with copper, and subsequently flattened and planarized to be even with the surrounding copper features. Therefore, with the application of the final finish, there is a solderable surface mount pad, also called an active pad, capable of passing signals to inner layers, eliminating the need to place vias on the surface layer for the purpose.
Vias Plugged with Conductive Fill
Some chips generate a lot of heat, which must be conducted away to prevent the chip from overheating. Placing thermal vias plugged with conductive fill under the chip helps in the process, as the metallic nature of the fill naturally wicks the heat away from the chip to the other side of the board, just as a radiator does. This technique is helpful even in cases where a chip draws high currents, as multiple vias plugged with conductive fill reduce the resistance of the track, thereby lowering the voltage drop between the voltage source and the pins of the chip.
Drawbacks of Conductive Fills
Vias filled with conductive fill generally present a different coefficient of thermal expansion (CTE) between the surrounding laminate and the metallic fill. With heat, metals expand much more rapidly than the surrounding laminate does, leading to a possible fracture between the pads and the hole wall. Therefore, where the purpose of the fill is only to reinforce the copper pad plated over the hole, designers using via-in-pad do not recommend the conductive filling process.
Designers often try to match the CTE of the conductive fill for vias with that of the surrounding material. This is important in the view of the board living out its life in a heating/cooling state, where the expansion and contraction of the materials can lead to stress fractures in vias and possible electrical opens in the worst cases. However, this consideration generally favors the non-conductive epoxies for via filling as their CTE matches that of the laminate more closely, making the PCB a more reliable product.
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How Reliable your PCBs are – Laminates Using High Tg Material

Construction methods of Printed circuit boards (PCBs) are essentially similar, although their constituent materials and the intrinsic quality of their surfaces may differ. These differences affect the durability and functionality of the PCB throughout its life and this may be critical to the application.
Essentially, the PCB should exhibit a reliable performance, whether it is in the manufacturing stage, in the assembly process, or in actual use. Apart from the additional costs incurred for correcting defects in the assembly process, there may be failures in actual use, resulting in claims. From this point of view, the cost of a high-quality PCB may be considered negligible.
Over the years, there has been considerable progress in the development of laminates used in the industry, leading to an improvement in the reliability of PCBs. Introduction of lead-free soldering, very high layer count, environmental issues, and electrical concerns have led to placing greater attention to the PCB materials.
To address the above issues, the laminate industry has introduced several products in the market. However, they all come with their own trade-offs, and there is no one perfect laminate to address all the issues. Users need to look at the pros and cons of each PCB laminate, and select the product that best fits their requirements.
Reliability of the PCB actually depends on the proper selection of the material for the laminate. Three parameters are crucial here—the glass transition temperature (Tg), Coefficient of thermal expansion (CTE), and the decomposition temperature (Td).
Glass Transition Temperature (Tg)—This is an important parameter for the base material, as it determines the temperature at which the resin matrix changes over from a firm, non-elastic condition to a soft, elastic one.
                                               Fig. 1: Glass Transition Temperature
The TG value for the base material actually sets an upper temperature boundary, where the resin matrix starts to decompose and subsequently the PCB delaminates. Therefore, Tg is not the maximum operational temperature for the PCB, but rather one the material can endure for only a very short duration.
Coefficient of Thermal Expansion (CTE)—this parameter shows the thermal expansion of the base material of the laminate, especially the absolute expansion in its z-direction. This value is of importance for the stability of vias. With a low CTE-z value, several reliability issues are reduced, such as cracks within the via, corner cracks, and pad lifting. Mostly, materials with a high Tg value also have a low CTE-z.
                                                 Fig. 2: CTE Before and Beyond Tg
                                          Fig. 3: CTE with Low Tg and High Tg Materials
Decomposition Temperature (Td)—this parameter depends on the energy of binding within the polymers in the resin system of the laminate, rather than on the laminate’s glass transition temperature. In the industry, this characteristic is usually indicated at one of two temperatures 260°C or 288°C, and expressed as the time to delamination of the tested material at either temperature. The time to delamination at a certain temperature is a very important indicator of the heat resistance of the lamination, considering the temperature profile for the lead-free solder reflow process often maximizes at 260°C.
Td indicates the temperature at which the base material loses 5% of its weight and is an important parameter of the thermal stability of the base material. Exceeding this temperature causes irreversible degradation and damages the material by decomposition.
Interrelation between the Parameters
Although knowing the individual numbers for each of the three parameters for a laminate is a good reference, their interdependence is more important. Although it is preferable to have a laminate with a higher Tg, a thermal expansion curve of the laminate offers a better understanding. If the thermal expansion curve shows an extremely high CTE beyond the Tg temperature, it reverses the benefits of a high Tg value.
                                                    Fig. 4: Materials with Different Tg
To understand this, consider the parts of the laminate where metals join the epoxy resin, such as copper traces and vias on the PCB. If the difference in the CTE between the two materials is high, there is a danger of the copper peeling away, and vias developing a crack in their barrels, once the temperature crosses Tg.
During lead-free soldering, the reflow temperature is typically 240-260°C, which is well beyond the Tg of most PCB materials. With very high CTE, even high Tg PCB materials will be unable to survive a soldering process. Therefore, a reliable material well suited to lead-free soldering must have a high Tg value along with a minimal transition of CTE values through Tg, followed with a relatively low CTE beyond the Tg value.
It is also important to look at the CTE value of the material in the x-y plane. Ideally, this value should match that of copper, but considering the complexities of laminates, it is much higher. Practically, a CTE value of 70 ppm/°C is satisfactory, although a lower number is better.
Although not much importance is placed on the Td value of a laminate, it can be a good indicator for the performance of a lead-free soldering process. As the temperature rises during the reflow process and approaches the Td, the resulting mass loss can develop stresses within the PCB material, and this can contribute to delamination. Therefore, materials with Td near the lead-free soldering temperatures may be a reliability concern. Although the material may not actually be losing enough mass for decomposition, the loss may be enough to cause a significant stress build-up.
Practical studies indicate materials with Td of 300°C often have problems with lead-free soldering, whereas materials with a Td of 400°C did not. At the same time, materials with lower Td also demonstrate a higher CTE, aggravating the issue at lead-free soldering temperatures.
Understanding Tg, CTE, and Td for a material and their interactions is very important for the reliability of lead-free soldering for a PCB, especially as it also involves the peel strength issues of the PCB at lead-free soldering temperatures.
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Trends in Surface Mount Technology and Its Relevance with PCB Surface Finish

It is necessary to mass-produce electronic circuit boards in a highly mechanical manner for ensuring the lowest cost of manufacturing. Traditional through-hole electronic components with leads did not lend themselves to this approach. Therefore, since the 1980s, virtually all electronics hardware is being mass-produced using surface mount technology (SMT). Compared to the through-hole technology (THT) used earlier, the surface mount devices (SMD) associated with SMT offer several advantages in terms of manufacturability and performance.

                                               Trends in Surface Mount Packaging
Almost all electronic components are available in forms suitable for surface mounting. SMDs do not have long leads that necessitates passing through the printed circuit board (PCB). Rather, they have very short leads that can be soldered directly to the copper pads on the PCB. Manufacturers use different types of SMD packaging, with the evolution tending towards increasing package and pin densities.

                                           Fig. 1: Trends in Surface Mount Packaging
The popular dual in line (DIP) packaging for ICs with two rows of pins for soldering has now diverged into the PGA, QFP, and TSOP type SMD packages. Compared to DIP, these packages have improved on the packaging density enormously. However, modern electronic equipment design demands even higher densities. As a consequence, we now see extremely dense SMD packaging in the form of BGAs, LQFPs, and TCPs. Now, SMD packages are converging towards chip scale packaging (CSP) types, offering better heat dissipation, higher package densities, and increased flexibility.
This trend towards miniaturization is visible for other passive components as well. All types of resistors, capacitors, and inductors are now available in small SMD packages. For instance, although the 0603 and 0402 packages are most commonly used, smaller sizes of 0201 are also available.
Trends in Soldering Techniques for SMT
Most countries have realized the hazards of using the element Lead in electronic equipment, and as a result, the use of lead and tin combination for production and use of solder has almost stopped. Instead, the industry now uses various forms of lead-free solder, although these have more stringent process requirements.
With the advent of new types of SMD packages, the trend in soldering techniques is also evolving. From the commonly used wave soldering for through-hole devices, the trend is towards use of non-contact soldering using infrared and hot gas reflow methods for SMDs.
Trends in Machinery for SMT
Mass production and high mechanization has replaced manual insertion of through-hole components with sophisticated pick-and-place machines for SMD components. These take the form of precision nozzles, intelligent feeder systems, multi-functional mounters, and 3-D molded interconnect devices.
Apart from advances in automated machinery used for SMT, the introduction of special SMD packages such as BGAs has necessitated use of specialized equipment for inspection of PCBs after assembly. Since it is visually impossible to inspect the underside of a BGA chip after it has been soldered, it is necessary to use X-rays to inspect the soldering. With high volumes of production and miniaturization, it is nearly impossible to inspect PCBs manually after assembly. Therefore, the current trend is towards in-circuit testers (ICT) and computerized automated test equipment using high-resolution digital cameras and special algorithms.
Relevance of Surface Finish of PCBs with SMT
The solderable surfaces of a PCB need protection from oxidation while the PCB moves from manufacturing to assembly. Oxidization of the copper surface prevents formation of a good solder joint. Quality of the surface finish affects first pass yield (FPY) and the final product reliability. Primary reasons for this involve non-uniform surface finish and poor solderability. Although there are other known factors for poor FPY, but surface finish issues are the main.
Typical surface finishes manufacturers use are:
  • Hot Air Solder Leveling (HASL)
  • Organic Solderability Preservatives (OSP)
  • Immersion Silver (ImAg)
  • Immersion Tin (ImSn)
  • Electroless Nickel/Immersion Gold (ENIG)
  • Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG)
Hot Air Solder Leveling (HASL) is the most common PCB finish, for both lead and lead-free compositions of solder. The process involves application of molten solder to the exposed pads in a vertical or horizontal panel orientation, with excess solder being blown away with a forced hot air knife. The typical thickness of HASL solder on the copper pad ranges from 0.3-1.5 mil, melting at 183°C for lead solder and at 228°C for lead-free solder, with a typical 12-month shelf life.

                                                      Fig. 2: Hot Air Solder Leveling
However, for HDI applications, the HASL process presents a highly variable topography, or inconsistent surface planarity because of the formation of solder beads/balls not conducive to SMT, especially for QFP and BGA packages. In addition, depending on the alloy used for lead-free solder, the HASL process may be aggressive on copper, reducing the shelf life. While the thermal shock may cause warping of the PCB, there can be PTH diameter issues and bridging of fine pitch traces with solder mask residue preventing HASL from flowing. In addition, contamination on the surface of the copper or resin residue on the laminate may cause poor bonding.
Organic Solderability Preservatives (OSP) is a low-cost transparent coating of organic material, which preserves the copper surface from oxidation until assembly. The process involves application in a dip tank with the PCB in a vertical position, or the use of a conveyorized chemical process, which leaves a very thin coating of the material, typically 100-4000 Angstroms thick. Although OSP is a flat, reliable planar surface, well suited to BGA and QFP packages, the shelf life is rather low, being typically 6 months or lower.

                                              Fig. 3: Organic Solderability Preservatives
OSP is difficult to inspect, and does not stand multiple reflows very well. This raises questions of reliability of exposed copper pads after assembly. As OSP is not conductive, ICT test pads need to be soldered.
Immersion Silver (ImAg) is a metallic solderability preservative, and the process deposits 8-15 micro inches of nearly pure silver on the copper surface. Although it provides a flat, planar surface, excellent solderability, and about 6-12 months of shelf life, immersion silver is sensitive to handling, packaging, electrical tests, and suffers from creep corrosion from salt and sulfur in the environment.

                                                            Fig. 4: Immersion Silver
Immersion Tin (ImSn) forms an intermetallic joint with copper to provide a uniform, dense coating with excellent hole-wall lubricity. As it is possible to engineer immersion tin to be non-porous and with very fine grain, it is the top choice for backplane panel assemblies requiring press-fit pin insertions.
However, immersion tin has a shelf life of 6 months, and is sensitive to handling. In addition, processing of immersion tin requires using Thiourea, a carcinogen with environmental issues.

                                                               Fig. 5: Immersion Tin
Electroless Nickel Immersion Gold (ENIG) is a complicated chemical process, involving nickel plating over the copper pad and subsequent gold plating over the nickel. The gold layer prevents the nickel from oxidizing during storage, while also providing low contact resistance, good wetting for solder, and excellent shelf life of typically 12 months. The flat planar surface is well suited for fine pitch devices such as BGA and QFP. Being conductive, ENIG offers good ICT contacts.

                                              Fig. 6: Electroless Nickel Immersion Gold
However, ENIG is an expensive process, with non-wetting issues if the process has not been executed properly. Slow intermetallic growth can result in poor joint reliability and strength.
Electroless Nickel Electroless Palladium immersion Gold (ENEPIG) is another complicated chemical process, involving depositing electroless nickel on the copper surface, followed by a coating of electroless palladium layer, topped with a layer of immersion gold. The triple layer helps to form a superior solder joint with lead-free solder. As the process allows a thinner layer of gold, the process is less expensive when compared to ENIG, although the extra process step offsets this. The flat planar surface suits fine pitch devices such as BGA and QFPs. As the shelf life is typically 12 months, ENEPIG is the fastest growing surface finish.

                               Fig. 7: Electroless Nickel Electroless Palladium Immersion Gold
PCB manufacturers prefer ENIG and ENEPIG to others because of the relative advantages the two techniques offer, although between the two, their advantages vary. ENIG is suitable for SMT, especially for BGA and other fine pitch components. The technology works well for lead-free soldering, and is highly reliable, which is why the flex PCB market prefers ENIG.
On the other hand, ENEPIG has a much wider acceptance and is suitable for multiple types of packages including THT, SMT, wire bonding, press fit, and more. Apart from being suitable for fine-pitch SMD components such as BGA and QFPs, ENEPIG is applicable to PCBs with different manufacturing technologies, requiring higher densities and reliability.

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